Ethernet (ETH): media access control (MAC) with DMA controller
RM0090
1178/1731
DocID018909 Rev 11
•
RDES3: Receive descriptor Word3
RDES3 contains the address pointer either to the second data buffer in the descriptor
or to the next descriptor, or it contains time stamp data.
Enhanced Rx DMA descriptors format with IEEE1588 time stamp
Enhanced descriptors (enabled with EDFE=1, ETHDMABMR bit 7), must be used if time
stamping is activated (TSE=1, ETH_PTPTSCR bit 0) or if IPv4 checksum offload is
activated (IPCO=1, ETH_MACCR bit 10).
Enhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors.
RDES0, RDES1, RDES2 and RDES3 have the same definitions as for normal receive
descriptors (refer to
). RDES4 contains extended status while
RDES6 and RDES7 hold the time stamp. RDES4, RDES5, RDES6 and RDES7 are defined
below.
When the Enhanced descriptor mode is selected, the software needs to allocate 32 bytes (8
DWORDS) of memory for every descriptor. When time stamping or IPv4 checksum offload
are not being used, the enhanced descriptor format may be disabled and the software can
use normal descriptors with the default size of 16 bytes.
31 30 29 28 27 26 25
24
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RBP2 / RTSH
rw rw rw rw rw rw rw
rw
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0
RBAP2 / RTSH:
Receive buffer 2 address pointer (next descriptor address) / Receive frame
time stamp high
These bits take on two different functions: the application uses them to indicate to the DMA
the location of where to store the data in memory, and then after transferring all the data the
DMA may use these bits to pass back time stamp data.
RBAP1:
When the software makes this descriptor available to the DMA (at the moment that
the OWN bit is set to 1 in RDES0), these bits indicate the physical address of buffer 2 when a
descriptor ring structure is used. If the second address chained (RDES1 [24]) bit is set, this address
contains the pointer to the physical memory where the next descriptor is present. If RDES1 [24] is
set, the buffer (next descriptor) address pointer must be bus width-aligned (RDES3[3, 2, or
1:0] = 0, corresponding to a bus width of 128, 64 or 32. LSBs are ignored internally.)
However, when RDES1 [24] is reset, there are no limitations on the RDES3 value, except for the
following condition: the DMA uses the configured value for its buffer address generation when the
RDES3 value is used to store the start of frame. The DMA ignores RDES3[3, 2, or 1:0]
(corresponding to a bus width of 128, 64 or 32) if the address pointer is to a buffer where the
middle or last part of the frame is stored.
RTSH:
Before it clears the OWN bit in RDES0, the DMA updates this field with the 32 most
significant bits of the time stamp captured for the corresponding receive frame (overwriting
the value for RBAP2). This field has the time stamp only if time stamping is activated and if
the Last segment control bit (LS) in the descriptor is set.
