USB on-the-go full-speed (OTG_FS)
RM0090
1256/1731
DocID018909 Rev 11
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Host port CSRs
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Host channel-specific registers
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Device-mode registers
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Device global registers
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Device endpoint-specific registers
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Power and clock-gating registers
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Data FIFO (DFIFO) access registers
Only the Core global, Power and clock-gating, Data FIFO access, and host port control and
status registers can be accessed in both host and device modes. When the OTG_FS
controller is operating in one mode, either device or host, the application must not access
registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is
generated and reflected in the Core interrupt register (MMIS bit in the OTG_FS_GINTSTS
register). When the core switches from one mode to the other, the registers in the new mode
of operation must be reprogrammed as they would be after a power-on reset.
