STMicroelectronics STM32F405, Reference Manual

Page: 1389 / 1731

DocID018909 Rev 11 1389/1731
RM0090 USB on-the-go high-speed (OTG_HS)
1529
Figure 413. CSR memory map
1. x = 5 in peripheral mode and x = 11 in host mode.
Global CSR map
These registers are available in both host and peripheral modes.
0000h
Core glob a l C S R s (1 Kbyte)
0400h
Ho s t mode C S R s (1 Kbyte)
0 8 00h
Device mode C S R s (1.5 Kbyte)
0E00h
Power a nd clock g a ting C S R s (0.5 Kbyte)
1000h
Device EP 0/Ho s t ch a nnel 0 FIFO (4 Kbyte)
2000h
Device EP1/Ho s t ch a nnel 1 FIFO (4 Kbyte)
3 000h
Device EP (x – 1)
(1)
/Ho s t ch a nnel (x – 1)
(1)
FIFO (4 Kbyte)
Device EP x
(1)
/Ho s t ch a nnel x
(1)
FIFO (4 Kbyte)
Re s erved
DFIFO
p
us h/pop
to thi s region
2 0000h
3 FFFFh
Direct a cce ss to d a t a FIFO RAM
for deb u gging (12 8 Kbyte)
DFIFO
deb
u g re a d/
write to thi s
region
a i15615b
Table 203. Core global control and status registers (CSRs)
Acronym
Address
offset
Register name
OTG_HS_GOTGCTL 0x000 OTG_HS control and status register (OTG_HS_GOTGCTL) on page 1393
OTG_HS_GOTGINT 0x004 OTG_HS interrupt register (OTG_HS_GOTGINT) on page 1395
OTG_HS_GAHBCFG 0x008 OTG_HS AHB configuration register (OTG_HS_GAHBCFG) on page 1397
OTG_HS_GUSBCFG 0x00C OTG_HS USB configuration register (OTG_HS_GUSBCFG) on page 1398
OTG_HS_GRSTCTL 0x010 OTG_HS reset register (OTG_HS_GRSTCTL) on page 1401
OTG_HS_GINTSTS 0x014 OTG_HS core interrupt register (OTG_HS_GINTSTS) on page 1404
OTG_HS_GINTMSK 0x018 OTG_HS interrupt mask register (OTG_HS_GINTMSK) on page 1408