Power controller (PWR)
RM0090
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DocID018909 Rev 11
5.3.6 Standby
mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex
®
-M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V
domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are
also switched off. SRAM and register contents are lost except for registers in the backup
domain (RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see
Table 29. Stop mode entry and exit (STM32F42xxx and STM32F43xxx)
Stop mode
Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– No interrupt or event is pending,
– SLEEPDEEP bit is set in Cortex
®
-M4 with FPU System Control register,
– PDDS bit is cleared in Power Control register (PWR_CR),
– Select the voltage regulator mode by configuring LPDS,
MRUDS, LPUDS
and UDEN bits
in PWR_CR (see
Table 28: Stop operating modes
On Return from ISR while:
– No interrupt is pending,
– SLEEPDEEP bit is set in Cortex
®
-M4 with FPU System Control register,
and
– SLEEPONEXIT = 1, and
– PDDS is cleared in PWR_CR1.
Note: To enter Stop mode, all EXTI Line pending bits (in
), all peripheral interrupts pending bits, the RTC Alarm
(Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time
stamp flags, must be reset. Otherwise, the Stop mode entry
procedure is ignored and program execution continues.
Mode exit
If WFI or Return from ISR was used for entry:
All EXTI lines configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx
on page 374
If WFE was used for entry and SEVONPEND = 0:
All EXTI Lines configured in event mode. Refer to
Wakeup event management on page 382
If WFE was used for entry and SEVONPEND = 1:
– Any EXTI lines configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 61: Vector table for STM32F405xx/07xx and STM32F415xx/17xx
on page 374
Table 62: Vector table for STM32F42xxx and
– Wakeup event: refer to
Section 12.2.3: Wakeup event management on
Wakeup latency
Refer to