DocID018909 Rev 11
RM0090
Flexible static memory controller (FSMC)
1588
Note:
PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the DATLAT field must be set to 0, so that the FSMC exits its
latency phase soon and starts sampling NWAIT from memory, then starts to read or write
when the memory is ready.
This method can be used also with the latest generation of synchronous Flash memories
that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the
specific Flash memory being used).
Bits 15:8
DATAST[7:0]:
Data-phase duration
These bits are written by software to define the duration of the data phase (refer to
to
), used in asynchronous accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
For each memory type and access mode data-phase duration, please refer to the respective
figure (
).
Example: Mode1, write access, DATAST=1: Data-phase duration= 1 = 2 HCLK clock
cycles.
Note: In synchronous accesses, this value is don't care.
Bits 7:4
ADDHLD[3:0]:
Address-hold phase duration
These bits are written by software to define the duration of the
address hold
phase (refer to
to
), used in mode D and multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration =1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address-hold phase duration, please refer to the respective figure
(
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
memory clock period duration.
Bits 3:0
ADDSET[3:0]:
Address setup phase duration
These bits are written by software to define the duration of the
address setup
phase (refer to
to
), used in SRAMs, ROMs and asynchronous NOR Flash and PSRAM
accesses:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address setup phase duration, please refer to the respective figure
(refer to
).
Note: In synchronous NOR Flash and PSRAM accesses, this value is don’t care.
