DocID018909 Rev 11
RM0090
Revision history
1726
19-Oct-2012
2
(continued)
FSMC:
Updated step b) in
Section 36.3.1: Supported memories and
Updated
Table 196: FSMC_BTRx bit fields
.
Changed Clock divide ration min in
NAND/PC Card access parameters
.
Updated case of synchronous accesses in
Changed minimum value for ADDSET to 0 in
Table 203
,
Table 206
,
Table 207
,
Table 209
, and
Table 210
.
Move note from
Figure 435: Mode1 write accesses
and
. Move note from
to
Figure 436: ModeA read accesses
Updated
Section : WAIT management in asynchronous accesses
Added register access in
Section 36.5.6: NOR/PSRAM control
Section 36.6.2: NAND Flash / PC Card supported
Removed caution note in
Section 36.6.1: External memory interface
.
Updated
Section 36.6.4: NAND Flash operations
Updated
Figure 453: Access to non ‘CE don’t care’ NAND-Flash
and
Section 36.6.5: NAND Flash pre-wait functionality
.
Updated access to I/O Space in
s
. Updated BUSTURN
b
it definition in
Section : SRAM/NOR-Flash chip-select timing registers 1..4
(FSMC_BTR1..4)
)
. Changed
b
its 16 to 19 to BUSTURN in
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)
DEBUG:
Updated
Section 38.4.3: Internal pull-up and pull-down on JTAG
Electronic signature
Updated
Section 39: Device electronic signature
introduction.
Updated REV_ID[15:0] to add revision Z in
.
Updated address and example in
Table 310. Document revision history (continued)
Date
Ver
s
ion
Chan
g
e
s