Flexible static memory controller (FSMC)
RM0090
1570/1731
DocID018909 Rev 11
SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)
Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank, used for SRAMs,
PSRAMs and NOR Flash memories. This register is active for write asynchronous access
only when the EXTMOD bit is set in the FSMC_BCRx register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Res.
ACCM
OD[2:0]
Reserved
BUSTURN[3:0]
DATAST[7:0]
ADDHLD[3:0]
ADDSET[3:0]
rw rw
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:30
Reserved, must be kept at reset value.
Bits 29:28
ACCMOD[2:0]:
Access mode.
Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are
taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.
00: access mode A
01: access mode B
10: access mode C
11: access mode D
Bits 27:20
Reserved, must be kept at reset value.
Bits 19:16
BUSTURN[3:0]
: Bus turnaround phase duration
The programmed bus turnaround delay is inserted between a an asynchronous write transfer and
any other asynchronous/synchronous read or write transfer to/from a static bank (for a read
operation, the bank can be the same or a different one; for a write operation, the bank can be
different except in r muxed or D mode).
In some cases, the bus turnaround delay is fixed, whatever the programmed BUSTURN values:
– No bus turnaround delay is inserted between two consecutive asynchronous write transfers to the
same static memory bank except in muxed and D mode.
– A bus turnaround delay of 2 FSMC clock cycles is inserted between:
–
Two consecutive synchronous write accesses (in burst or single mode) to the same bank.
–
A synchronous write transfer (in burst or single mode) and an asynchronous write or read
transfer to/from static a memory bank.
– A bus turnaround delay of 3 FSMC clock cycles is inserted between:
–
Two consecutive synchronous write accesses (in burst or single mode) to different static
banks.
–
A synchronous write transfer (in burst or single mode) and a synchronous read from the
same or from a different bank.
0000: BUSTURN phase duration = 0 HCLK clock cycle added
...
1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
