DocID018909 Rev 11
RM0090
Flexible memory controller (FMC)
1669
The address management depends on the next AHB request:
•
Next AHB request is sequential (AHB Burst)
In this case, the SDRAM controller increments the address.
•
Next AHB request is not sequential
–
If the new read request targets the same row or another active row, the new
address is passed to the memory and the master is stalled for the CAS latency
period, waiting for the new data from memory.
–
If the new read request does not target an active row, the SDRAM controller
generates a Precharge command, activates the new row, and initiates a read
command.
If the RURST is reset, the read FIFO is not used.
Row and bank boundary management
When a read or write access crosses a row boundary, if the next read or write access is
sequential and the current access was performed to a row boundary, the SDRAM controller
executes the following operations:
1.
Precharge of the active row,
2. Activation of the new row
3. Start of a read/write command.
At a row boundary, the automatic activation of the next row is supported for all columns and
data bus width configurations.
If necessary, the SDRAM controller inserts additional clock cycles between the following
commands:
•
Between Precharge and Active commands to match TRP parameter (only if the next
access is in a different row in the same bank),
•
Between Active and Read commands to match the TRCD parameter.
These parameters are defined into the FMC_SDTRx register.
and
for read and burst write access crossing a row
boundary.
