Power controller (PWR)
RM0090
120/1731
DocID018909 Rev 11
by a dedicated bit, the BRE control bit of the PWR_CSR register (see
power control/status register (PWR_CSR) for STM32F405xx/07xx and
STM32F415xx/17xx
).
The backup SRAM is not mass erased by an tamper event. When the Flash memory is read
protected, the backup SRAM is also read protected to prevent confidential data, such as
cryptographic private key, from being accessed. When the protection level change from
level 1 to level 0 is requested, the backup SRAM content is erased.
Figure 11. Backup domain
5.1.3
Voltage regulator for STM32F405xx/07xx and STM32F415xx/17xx
An embedded linear voltage regulator supplies all the digital circuitries except for the backup
domain and the Standby circuitry. The regulator output voltage is around 1.2 V.
This voltage regulator requires one or two external capacitors to be connected to one or two
dedicated pins, V
CAP_1
and V
CAP_2
available in all packages. Specific pins must be
connected either to V
SS
or V
DD
to activate or deactivate the voltage regulator. These pins
depend on the package.
When activated by software, the voltage regulator is always enabled after Reset. It works in
three different modes depending on the application modes.
•
In
Run mode
, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can
be scaled by software to different voltage values:
Scale 1 or scale 2 can be configured on the fly through VOS (bit 15 of the
PWR_CR register).
The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency.
•
In
Stop mode,
the main regulator or the low-power regulator supplies to the 1.2 V
domain, thus preserving the content of registers and internal SRAM. The voltage
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