Ethernet (ETH): media access control (MAC) with DMA controller
RM0090
1118/1731
DocID018909 Rev 11
160 ns each, and the minimum period for MDC must be 400 ns. In idle state the SMI
management interface drives the MDC clock signal low.
•
MDIO: data input/output bitstream to transfer status information to/from the PHY device
synchronously with the MDC clock signal
Figure 351. SMI interface signals
SMI frame format
The frame structure related to a read or write operation is shown in
Table 13
, the order of bit
transmission must be from left to right.
The management frame consists of eight fields:
•
Preamble
: each transaction (read or write) can be initiated with the preamble field that
corresponds to 32 contiguous logic one bits on the MDIO line with 32 corresponding
cycles on MDC. This field is used to establish synchronization with the PHY device.
•
Start
: the start of frame is defined by a <01> pattern to verify transitions on the line
from the default logic one state to zero and back to one.
•
Operation
: defines the type of transaction (read or write) in progress.
•
PADDR
: the PHY address is 5 bits, allowing 32 unique PHY addresses. The MSB bit of
the address is the first transmitted and received.
•
RADDR
: the register address is 5 bits, allowing 32 individual registers to be addressed
within the selected PHY device. The MSB bit of the address is the first transmitted and
received.
•
TA
: the turn-around field defines a 2-bit pattern between the RADDR and DATA fields
to avoid contention during a read transaction. For a read transaction the MAC controller
drives high-impedance on the MDIO line for the 2 bits of TA. The PHY device must
drive a high-impedance state on the first bit of TA, a zero bit on the second one.
Table 185. Management frame format
Management frame fields
Preamble
(32 bits)
Start
Operation PADDR RADDR TA
Data (16 bits)
Idle
Read
1... 1
01
10
ppppp
rrrrr
Z0
ddddddddddddddd
Z
Write
1... 1
01
01
ppppp
rrrrr
10
ddddddddddddddd
Z
6700&8
0',2
0'&
([WHUQDO
3+<
DLE
-!
#
