STMicroelectronics STM32F405, Reference Manual

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Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090
206/1731 DocID018909 Rev 11
6.3.24 RCC PLL configuration register (RCC_PLLSAICFGR)
Address offset: 0x88
Reset value: 0x2400 3000
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLSAI clock outputs according to the formulas:
•
f
(VCO clock)
= f
(PLLSAI clock input)
× (PLLSAIN / PLLM)
•
f
(PLLSAI1 clock output)
= f
(VCO clock)
/ PLLSAIQ
•
f
(PLL LCD clock output)
= f
(VCO clock)
/ PLLSAIR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PLLSAIR PLLSAIQ
Reserved
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PLLSAIN
Reserved
rw rw rw rw rw rw rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLSAIR: PLLSAI division factor for LCD clock
Set and reset by software to control the LCD clock frequency.
These bits should be written when the PLLSAI is disabled.
LCD clock frequency = VCO frequency / PLLSAIR with 2
≤ PLLSAIR ≤ 7
000: PLLSAIR = 0, wrong configuration
001: PLLSAIR = 1, wrong configuration
010: PLLSAIR = 2
...
111: PLLSAIR = 7
Bits 27:24 PLLSAIQ: PLLSAI division factor for SAI1 clock
Set and reset by software to control the frequency of SAI1 clock.
These bits should be written when the PLLSAI is disabled.
SAI1 clock frequency = VCO frequency / PLLSAIQ with 2
≤ PLLSAIQ ≤ 15
0000: PLLSAIQ = 0, wrong configuration
0001: PLLSAIQ = 1, wrong configuration
...
0010: PLLSAIQ = 2
0011: PLLSAIQ = 3
0100: PLLSAIQ = 4
0101: PLLSAIQ = 5
...
1111: PLLSAIQ = 15