DocID018909 Rev 11
RM0090
Flexible memory controller (FMC)
1669
Mode D - asynchronous access with extended address
Figure 465. ModeD read access waveforms
Table 274. FMC_BWTRx bit fields
Bit No.
Bit name
Value to set
31:30
Reserved
0x0
29-28
ACCMOD
0x2
27-24
DATLAT
Don’t care
23-20
CLKDIV
Don’t care
19-16
BUSTURN
Time between NEx high to NEx low (BUSTURN HCLK)
15-8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for
write accesses.
7-4
ADDHLD
Don’t care
3-0
ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
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