DocID018909 Rev 11
881/1731
RM0090
Serial peripheral interface (SPI)
918
Figure 256. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of
continuous transfers
Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1)
In this mode, the procedure is similar to the procedure in Transmit-only mode except that
the BIDIMODE and BIDIOE bits both have to be set in the SPI_CR2 register before enabling
the SPI.
Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1)
In this mode, the procedure can be reduced as described below (see
1.
Set the RXONLY bit in the SPI_CR2 register.
2. Enable the SPI by setting the SPE bit to 1:
a) In master mode, this immediately activates the generation of the SCK clock, and
data are serially received until the SPI is disabled (SPE=0).
b) In slave mode, data are received when the SPI master device drives NSS low and
generates the SCK clock.
3. Wait until RXNE=1 and read the SPI_DR register to get the received data (this clears
the RXNE bit). Repeat this operation for each data item to be received.
This procedure can also be implemented using dedicated interrupt subroutines launched at
each rising edge of the RXNE flag.
Note:
If it is required to disable the SPI after the last transfer, follow the recommendation
described in
Section 28.3.8: Disabling the SPI on page 886
.
0xF1
Tx b
u
ffer
TXE fl
a
g
0xF2
B
S
Y fl
a
g
0xF
3
software writes
0xF1 into
SPI_DR
software waits
until TXE=1 and
writes 0xF2 into
SPI_DR
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et by h
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red by
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et by h
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red by
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et by h
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et by h
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S
CK
re
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et by h
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Ex
a
mple in
s
l
a
ve mode with CPOL=1, CPHA=1
(write to
S
PI_DR)
MI
S
O/MO
S
I (o
u
t)
DATA 1 = 0xF1
DATA 2 = 0xF2
DATA
3
= 0xF
3
software waits
until TXE=1 and
writes 0xF3 into
SPI_DR
software waits until BSY=0
software waits until TXE=1
b0 b1 b2 b
3
b4 b5 b6 b7 b0 b1 b2 b
3
b4 b5 b6 b7 b0 b1 b2 b
3
b4 b5 b6 b7
a
i17
3
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