USB on-the-go high-speed (OTG_HS)
RM0090
1502/1731
DocID018909 Rev 11
d) The OTG_HS host generates the CHH interrupt after successfully transmitting the
start split IN token.
e) In response to the CHH interrupt, set the COMPLSPLT bit in HCSPLT2 to send the
complete split.
f)
As soon as the packet is received successfully, the OTG_HS host starts writing the
data to the system memory.
g) The OTG_HS host generates the CHH interrupt after transferring the received
data to the system memory. In response to the CHH interrupt, de-allocate the
channel or reinitialize the channel for the next start split.
35.13.6 Device programming model
Endpoint initialization on USB reset
1.
Set the NAK bit for all OUT endpoints
–
SNAK = 1 in OTG_HS_DOEPCTLx (for all OUT endpoints)
2. Unmask the following interrupt bits
–
INEP0 = 1 in OTG_HS_DAINTMSK (control 0 IN endpoint)
–
OUTEP0 = 1 in OTG_HS_DAINTMSK (control 0 OUT endpoint)
–
STUP = 1 in DOEPMSK
–
XFRC = 1 in DOEPMSK
–
XFRC = 1 in DIEPMSK
–
TOC = 1 in DIEPMSK
3. Set up the Data FIFO RAM for each of the FIFOs
–
Program the OTG_HS_GRXFSIZ register, to be able to receive control OUT data
and setup data. If thresholding is not enabled, at a minimum, this must be equal to
1 max packet size of control endpoint 0 + 2 DWORDs (for the status of the control
OUT data packet) + 10 DWORDs (for setup packets).
–
Program the OTG_HS_TX0FSIZ register (depending on the FIFO number
chosen) to be able to transmit control IN data. At a minimum, this must be equal to
1 max packet size of control endpoint 0.
4. Program the following fields in the endpoint-specific registers for control OUT endpoint
0 to receive a SETUP packet
–
STUPCNT = 3 in OTG_HS_DOEPTSIZ0 (to receive up to 3 back-to-back SETUP
packets)
5. In DMA mode, the DOEPDMA0 register should have a valid memory address to store
any SETUP packets received.
At this point, all initialization required to receive SETUP packets is done.
