DocID018909 Rev 11
RM0090
USB on-the-go high-speed (OTG_HS)
1529
The following transfer parameters can be programmed:
•
Transfer size in bytes
•
Number of packets constituting the overall transfer size
•
Initial data PID
Host channel status/interrupt
The host channel-x interrupt register (HCINTx) indicates the status of an endpoint with
respect to USB- and AHB-related events. The application must read these register when the
host channels interrupt bit in the core interrupt register (HCINT bit in OTG_HS_GINTSTS) is
set. Before the application can read these registers, it must first read the host all channels
interrupt (HCAINT) register to get the exact channel number for the host channel-x interrupt
register. The application must clear the appropriate bit in this register to clear the
corresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt
source of each channel are also available in the OTG_HS_HCINTMSK-x register.
The host core provides the following status checks and interrupt generation:
•
Transfer completed interrupt, indicating that the data transfer is complete on both the
application (AHB) and USB sides
•
Channel stopped due to transfer completed, USB transaction error or disable
command from the application
•
Associated transmit FIFO half or completely empty (IN endpoints)
•
ACK response received
•
NAK response received
•
STALL response received
•
USB transaction error due to CRC failure, timeout, bit stuff error, false EOP
•
Babble error
•
Frame overrun
•
Data toggle error
35.6.4 Host
scheduler
The host core features a built-in hardware scheduler which is able to autonomously re-order
and manage the USB the transaction requests posted by the application. At the beginning of
each frame the host executes the periodic (isochronous and interrupt) transactions first,
followed by the nonperiodic (control and bulk) transactions to achieve the higher level of
priority granted to the isochronous and interrupt transfer types by the USB specification.
The host processes the USB transactions through request queues (one for periodic and one
for nonperiodic). Each request queue can hold up to 8 entries. Each entry represents a
pending transaction request from the application, and holds the IN or OUT channel number
along with other information to perform a transaction on the USB. The order in which the
requests are written to the queue determines the sequence of the transactions on the USB
interface.
At the beginning of each frame, the host processes the periodic request queue first, followed
by the nonperiodic request queue. The host issues an incomplete periodic transfer interrupt
(IPXFR bit in OTG_HS_GINTSTS) if an isochronous or interrupt transaction scheduled for
the current frame is still pending at the end of the current frame. The OTG HS core is fully
responsible for the management of the periodic and nonperiodic request queues.The
periodic transmit FIFO and queue status register (HPTXSTS) and nonperiodic transmit
