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789
PLC Setup
Appendix G
2
2-3
2-3-6
Received
Bytes
256 bytes
256 bytes
Every cycle
165
(CP1L
EM-type
CPU Unit)
00 to
07
00 hex
1 byte
01 hex
:
:
255 bytes
FF hex
2-3-7
Set End
Code
0x0000
0x0000
Every cycle
164
(CP1L
EM-type
CPU Unit)
00 to
07
00 hex
:
:
0x00FF
FF hex
2-3-8
Delay
0: 0
×
10 ms
0: 0
×
10 ms
Every cycle
162
(CP1L
EM-type
CPU Unit)
00 to
15
0000 hex
:
:
9999: 9999
×
10 ms
270F hex
2-4
ToolBus (peripheral bus)
2-4-1
Baud
9,600 bps
9,600 bps
Every cycle
161
(CP1L
EM-type
CPU Unit)
00 to
07
00 or
06 hex
19,200 bps
07 hex
38,400 bps
08 hex
57,600 bps
09 hex
115,200 bps
0A hex
2-5
Serial Gateway
2-5-1
Baud
9,600 bps
300 bps
Every cycle
161
(CP1L
EM-type
CPU Unit)
00 to
07
01 hex
600 bps
02 hex
1,200 bps
03 hex
2,400 bps
04 hex
4,800 bps
05 hex
9,600 bps
00 or
06 hex
19,200 bps
07 hex
38,400 bps
08 hex
57,600 bps
09 hex
115,200 bps
0A hex
2-5-2
Format
(data
length,
stop bits,
parity)
7,2,E: 7-bit
data, 2 stop
bits, even parity
7,2,E: 7-bit data, 2 stop
bits, even parity
Every cycle
160
(CP1L
EM-type
CPU Unit)
00 to
03
0 hex
7,2,O: 7-bit data, 2 stop
bits, odd parity
1 hex
7,2,N: 7-bit data, 2 stop
bits, no parity
2 hex
7,1,E: 7-bit data, 2 stop
bits, even parity
4 hex
7,1,O: 7-bit data, 1 stop
bit, odd parity
5 hex
7,1,N: 7-bit data, 1 stop
bit, no parity
6 hex
8,2,E: 8-bit data, 2 stop
bits, even parity
8 hex
8,2,O: 8-bit data, 2 stop
bits, odd parity
9 hex
8,2,N: 8-bit data, 2 stop
bits, no parity
A hex
8,1,E: 8-bit data, 1 stop
bit, even parity
C hex
8,1,O: 8-bit data, 1 stop
bit, odd parity
D hex
8,1,N: 8-bit data, 1 stop
bit, no parity
E hex
2-5-3
Response
Timeout
50:
50
×
100 ms =
5 s
50: 50
×
100 ms = 5 s
Every cycle
167
(CP1L
EM-type
CPU Unit)
08 to
15
00 hex
1: 1
×
100 ms
01 hex
:
:
255: 255
×
100 ms
FF hex
Name
Default
Settings
When setting is read
by CPU Unit
Internal
address
Bits
Settings
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......