705
Auxiliary Area Allocations by Address
Appendix D
A276
and
A277
All
Pulse Output
0 PV
Contain the number of pulses output
from the corresponding pulse output
port.
PV range: 8000 0000 to 7FFF FFFF
hex
(-2,147,483,648 to 2,147,483,647)
When pulses are being output in the
CW direction, the PV is incremented
by 1 for each pulse.
When pulses are being output in the
CCW direction, the PV is decre-
mented by 1 for each pulse.
PV after overflow: 7FFF FFFF hex
PV after underflow: 8000 0000 hex
A277 contains the leftmost 4 digits
and A276 contains the rightmost 4
digits of the pulse output 0 PV.
A279 contains the leftmost 4 digits
and A278 contains the rightmost 4
digits of the pulse output 1 PV.
Cleared when operation starts.
Note
If the coordinate system is
relative coordinates (unde-
fined origin), the PV will be
cleared to 0 when a pulse
output starts, i.e. when a
pulse output instruction
(SPED(885), ACC(888), or
PLS2(887)) is executed.
---
---
Cleared
Refreshed
each cycle
during
oversee
process.
Refreshed
when the
INI(880)
instruction
is executed
(PV
change).
---
A278
and
A279
All
Pulse Output
1 PV
Cleared
---
A280
00
Pulse Output
0 Accel/Decel
Flag
This flag will be ON when pulses are
being output from pulse output 0
according to an ACC(888) or
PLS2(887) instruction and the output
frequency is being changed in steps
(accelerating or decelerating).
Cleared when operation starts or
stops.
OFF: Constant speed
ON: Accelerating or decelerating
---
---
Cleared
Refreshed
each cycle
during
oversee
process.
---
01
Pulse Output
0 Overflow/
Underflow
Flag
This flag indicates when an overflow
or underflow has occurred in the
pulse output 0 PV.
Cleared when operation starts.
OFF: Normal
ON: Overflow or underflow
---
---
Cleared
Cleared
when the
PV is
changed
by the
INI(880)
instruction.
Refreshed
when an
overflow or
underflow
occurs.
---
Address
Name
Function
Settings
Status
after
mode
change
Status
at star-
tup
Write
timing
Related
flags, set-
tings
Words
Bits
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......