384
Interrupt Functions
Section 8-1
Procedure
Note
The input interrupt (counter mode) function is one of the input interrupt func-
tions and executes an interrupt based on the pulse count. If the input pulse
frequency is too high, interrupts will occur too frequently and prevent normal
cyclic task processing. In this case, cycle time too long errors may occur or
the pulse input may not be read.
The maximum total frequency of the counter-mode interrupt inputs is 5 kHz.
Even in this case, the high frequencies may adversely affect other devices’
operation or the system load, so check the system’s operation thoroughly
before using the counters at high frequencies.
PLC Setup
The procedures for using the CX-Programmer to set the PLC Setup are the
same as the procedures for input interrupts (direct mode). Refer to 8-1-2 Input
Interrupts (Direct Mode) for details.
Writing the Ladder
Program
MSKS(690) Settings
The MSKS(690) instruction must be executed in order to use input interrupts.
The settings made with MSKS(690) are enabled with just one execution, so in
general execute MSKS(690) in just one cycle using an up-differentiated condi-
tion.
MSKS(690) has the following two functions and three of the instructions are
used in combination. If up-differentiated input pulses are being used, the first
MSKS(690) instruction can be omitted since the input is set for up-differentia-
tion by default.
Select the input interrupts (counter
mode).
• Determine the inputs to be used for input
interrupts and corresponding task numbers.
↓
Wire the inputs.
• Wire the inputs.
↓
Set the PLC Setup.
• Use the CX-Programmer to select the inter-
rupt inputs in the PLC Setup.
↓
Set the counter SVs.
• Set the interrupt counter SVs in the corre-
sponding AR Area words.
↓
Write the ladder program.
• Write the programs for the corresponding
interrupt task numbers.
• Use MSKS(690) to specify up-differentiation
or down-differentiation.
• Use MSKS(690) to enable input interrupts (in
counter mode).
N
S
N
S
Execution condition
2. Enables or disables the input interrupt.
1. Specifies up-differentiated or
down-differentiated inputs.
MSKS(690)
MSKS(690)
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
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Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
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