Omron CP1L-EL20DR-D, Operation Manual

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Auxiliary Area Allocations by Address Appendix D
A528 08 to 15 Serial Port 1
Error Code
(CP1L EM-
type CPU
Units)
These flags indicate what kind of
error has occurred at the serial port 1
of a CP1L EM-type CPU Unit; they
are automatically turned OFF when
the serial port 1 is restarted.
(These flags are not valid in periph-
eral bus mode and only bit 5 is valid
in NT Link mode.)
PLC Link Polling Unit:
Bit 13: ON for timeout error.
PLC Link Polled Unit:
Bit 11: ON for framing error.
Bit 12: ON for overrun error.
Bit 13: ON for timeout error.
These bits can be cleared by the CX-
Programmer. Bits 08 and 09:
Not used.
Bit 10: ON for
parity error.
Bit 11: ON for
framing error.
Bit 12: ON for
overrun error.
Bit 13: ON for
timeout error.
Bits 14 and 15:
Not used. Retained Cleared --- ---
A529 All FAL/FALS
Number for
System
Error Simu-
lation Set a dummy FAL/FALS number to
use to simulate the system error
using FAL(006) or FALS(007).
When FAL(006) or FALS(007) is
executed and the number in A529 is
the same as the one specified in the
operand of the instruction, the sys-
tem error given in the operand of the
instruction will be generated instead
of a user-defined error. 0001 to 01FF
hex: FAL/FALS
numbers 1 to
511
0000 or 0200
to FFFF hex:
No FAL/FALS
number for sys-
tem error simu-
lation. (No error
will be gener-
ated.) Retained Cleared --- ---
A531 00 High-speed
Counter 0
Reset Bit When the reset method is set to
Phase-Z Software reset, the
corresponding high-speed counter’s
PV will be reset if the phase-Z signal
is received while this bit is ON.
When the reset method is set to Soft-
ware reset, the corresponding high-
speed counter’s PV will be reset in
the cycle when this bit turns ON. --- Retained Cleared --- ---
01 High-speed
Counter 1
Reset Bit --- Retained Cleared --- ---
08 High-speed
Counter 0
Gate Bit When a counter’s Gate Bit is ON, the
counter's PV will not be changed
even if pulse inputs are received for
the counter.
When the bit is turned OFF again,
counting will restart and the high-
speed counter’s PV will be
refreshed.
When the reset method is set to
Phase-Z Software reset, the
Gate Bit is disabled while the corre-
sponding Reset Bit (A531.00 or
A531.01) is ON. --- Retained Cleared --- ---
09 High-speed
Counter 1
Gate Bit --- Retained Cleared --- ---
A532 All Interrupt
Counter 0
Counter SV Used for interrupt input 0 in counter
mode.
Sets the count value at which the
interrupt task will start. Interrupt task
140 will start when interrupt counter
0 has counted this number of pulses.
Retained when operation starts. --- Retained Retained --- ---
A533 All Interrupt
Counter 1
Counter SV Used for interrupt input 1 in counter
mode.
Sets the count value at which the
interrupt task will start. Interrupt task
141 will start when interrupt counter
1 has counted this number of pulses. --- Retained Retained --- ---
A534 All Interrupt
Counter 2
Counter SV Used for interrupt input 2 in counter
mode.
Sets the count value at which the
interrupt task will start. Interrupt task
142 will start when interrupt counter
2 has counted this number of pulses. --- Retained Retained --- ---
Addresses Name Function Settings Status
after
mode
change
Status at
startup
Write
timing
Related
Flags,
Settings
Word Bits