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54
CPU Unit Operation
Section 2-4
(4) Using instructions with the immediate refresh option, instruction execu-
tion time will be increased, increasing the overall cycle time. Be sure to
confirm that this will not adversely affect system operation.
IORF(097) Refreshing
When IORF(097) (I/O REFRESH) is executed, the I/O bits in the specified
range of words are refreshed. IORF(097) can be used for CP-series Expan-
sion Units and CP-series Expansion I/O Units.
If high-speed response is required from input to output, execute IORF(097)
before and after the relevant instructions.
Note
IORF(097) has a relatively long execution time which increases with the num-
ber of words being refreshed. Be sure to consider the affect of this time on the
overall cycle time. Refer to the CP Series Programmable Controllers Program-
ming Manual for instruction execution times.
2-4-4
Initialization at Startup
The following initializing processes will be performed once each time the
power is turned ON.
• Confirm mounted Units and I/O allocations.
• Clear the non-holding areas of I/O memory according to the status of the
IOM Hold Bit. (See note 1.)
• Clear forced status according to the status of the Forced Status Hold Bit.
(See note 2.)
• Automatically transfer data from the Memory Cassette if one is mounted
and automatic transfer at startup is specified.
• Perform self-diagnosis (user memory check).
• Restore the user program. (See note 3.)
Note
(1) The I/O memory is held or cleared according to the status of the IOM Host
Bit and the setting for IOM Hold Bit Status at Startup in the PLC Setup
(read only when power is turned ON).
Note
When the mode is changed between PROGRAMMING mode and
RUN or MONITOR mode, I/O memory initialization is according to
the status of the IOM Hold Bit at that time.
IORF
St
E
IORF
2
5
Example
St
: Starting word
E
: End word
All the words from St to E, inclusive
are refreshed.
Here, the four words from CIO 2
to CIO 5 are refreshed.
Auxiliary bit
PLC Setup setting
IOM Hold Bit (A500.12)
Clear (OFF)
Hold (ON)
IOM Hold Bit Status
at Startup
Clear
(OFF)
At power ON: Clear
At mode change: Clear
At power ON: Clear
At mode change: Hold
Hold
(ON)
At power ON: Hold
At mode change: Hold
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......