![Omron CP1L-EL20DR-D Operation Manual Download Page 161](http://html1.mh-extra.com/html/omron/cp1l-el20dr-d/cp1l-el20dr-d_operation-manual_743755161.webp)
127
Index Registers
Section 4-11
Example
This example shows how to store the PLC memory address of a word (CIO 2)
in an Index Register (IR0), use the Index Register in an instruction, and use
the auto-increment variation.
MOVR(560)
2
IR0
Stores the PLC memory address of
CIO 2 in IR0.
MOV(021)
#0001
,IR0
Writes #0001 to the PLC memory ad-
dress contained in IR0.
MOV(021)
#0020
+1,IR0 Reads the content of IR0, adds 1,
and writes #0020 to that PLC memo-
ry address.
Note
The PLC memory addresses are listed in the diagram above, but it isn’t nec-
essary to know the PLC memory addresses when using Index Registers.
Since some operands are treated as word data and others are treated as bit
data, the meaning of the data in an Index Register will differ depending on the
operand in which it is used.
1,2,3...
1.
Word Operand:
MOVR(560)
0000
IR2
MOV(021)
D0
, IR2
When the operand is treated as a word, the contents of the Index Register
are used “as is” as the PLC memory address of a word.
In this example MOVR(560) sets the PLC memory address of CIO 2 in IR2
and the MOV(021) instruction copies the contents of D0 to CIO 2.
2.
Bit Operand:
MOVR(560)
000013
,IR2
SET
+5 , IR2
When the operand is treated as a bit, the leftmost 7 digits of the Index Reg-
ister specify the word address and the rightmost digit specifies the bit num-
ber. In this example, MOVR(560) sets the PLC memory address of CIO 13
(0C00D hex) in IR2. The SET instruction adds +5 from bit 13 (D hex) to this
PLC memory address, so it turns ON bit CIO 1.02.
Index Register
Initialization
The Index Registers will be cleared in the following cases:
1.
When the operating mode is changed from PROGRAM to RUN or MONI-
TOR mode or vice-versa
2.
When the power is cycled
#0001
#0020
Regular
data area
address
I/O memory
PLC memory
address
MOVE TO REGISTER instruction
MOVR(560) 0002 IR0
Pointer
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......