35
Specifications
Section 2-2
Setting Output Functions Using Instructions and PLC Setup
Note
The bits CIO 101.04 to CIO 101.07 cannot be used for CPU Units with 30 I/O
points.
The bits CIO 101.00 to CIO 101.07 cannot be used for CPU Units with 20 I/O
points.
Input Specifications
Normal Inputs
Address
When the
instructions to
the right are not
executed
When a pulse output
instruction (SPED, ACC,
PLS2, or ORG) is executed
When origin searches are
enabled in the PLC Setup,
and an origin search is
executed with ORG
instruction
When the PWM
instruction is
executed
Word
Bit
Normal outputs
Fixed duty ratio pulse output
Variable duty ratio
pulse output
CW/CCW
Pulse plus
direction
+ When the origin search
function is used
PWM output
CIO 100
00
Normal output 0
Pulse output 0
(CW)
Pulse output 0
(pulse)
---
---
01
Normal output 1
Pulse output 0
(CCW)
Pulse output 0
(direction)
---
PWM output 0
02
Normal output 2
Pulse output 1
(CW)
Pulse output 1
(pulse)
---
---
03
Normal output 3
Pulse output 1
(CCW)
Pulse output 1
(direction)
---
PWM output 1
04
Normal output 4
---
---
Origin search 0 (Error counter
reset output)
---
05
Normal output 5
---
---
Origin search 1 (Error counter
reset output)
---
06
Normal output 6
---
---
---
---
07
Normal output 7
---
---
---
---
CIO 101
00
Normal output 8
---
---
---
---
01
Normal output 9
---
---
---
---
02
Normal output 10 ---
---
---
---
03
Normal output 11 ---
---
---
---
04
Normal output 12 ---
---
---
---
05
Normal output 13 ---
---
---
---
06
Normal output 14 ---
---
---
---
07
Normal output 15 ---
---
---
---
Item
Specification
High-speed Counter Inputs
Interrupt Inputs and
Quick-response Inputs
Normal inputs
CIO 0.00 to CIO 0.03
CIO 0.04 to CIO 0.09 (See
note 1.)
CIO 0.10 to CIO 0.11 and
CIO 1.00 to CIO 1.11 (See
note 2.)
Input voltage
24 VDC
+10%
/
−
15%
Applicable inputs
2-wire and 3-wire sensors
Input impedance
3.0 k
Ω
3.0 k
Ω
4.7 k
Ω
Input current
7.5 mA typical
7.5 mA typical
5 mA typical
ON voltage
17.0 VDC min.
17.0 VDC min.
14.4 VDC min.
OFF voltage/current
1 mA max. at 5.0 VDC max.
1 mA max. at 5.0 VDC max.
1 mA max. at 5.0 VDC max.
ON delay
2.5
μ
s max.
50
μ
s max.
1 ms max. (See note 3.)
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......