126
Index Registers
Section 4-11
(2) When an Instruction Execution Error or an Illegal Access Error is gener-
ated during the execution of a certain instruction, the auto-increment/dec-
rement for the rest Index Registers of the instruction will not execute.
(3) An Illegal Access Error will be generated when indirectly addressing
memory in D10000 to D31999 with Index Registers for CPU Units with 20
I/O Points.
The following table shows the variations available when indirectly addressing
I/O memory with Index Registers. (IR
@
represents an Index Register from IR0
to IR15.)
Variation
Function
Syntax
Example
Indirect addressing
The content of IR
@
is treated as
the PLC memory address of a bit
or word.
,IR
@
LD ,IR0
Loads the bit at the PLC
memory address contained
in IR0.
Indirect addressing
with constant offset
The constant prefix is added to the
content of IR
@
and the result is
treated as the PLC memory
address of a bit or word.
The constant may be any integer
from –2,048 to 2,047.
Constant ,IR
@
(Include a + or –
in the constant.)
LD +5,IR0
Adds 5 to the contents of IR0
and loads the bit at that PLC
memory address.
Indirect addressing
with DR offset
The content of the Data Register
is added to the content of IR
@
and
the result is treated as the PLC
memory address of a bit or word.
DR
@
,IR
@
LD
DR0,IR0
Adds the contents of DR0 to
the contents of IR0 and
loads the bit at that PLC
memory address.
Indirect addressing
with auto-increment
After referencing the content of
IR
@
as the PLC memory address
of a bit or word, the content is
incremented by 1 or 2.
Increment by 1:
,IR
@
+
Increment by 2:
,IR
@
++
LD , IR0++
Loads the bit at the PLC
memory address contained
in IR0 and then increments
the content of IR0 by 2.
Indirect addressing
with auto-decrement
The content of IR
@
is decre-
mented by 1 or 2 and the result is
treated as the PLC memory
address of a bit or word.
Decrement by 1:
,–IR
@
Decrement by 2:
,– –IR
@
LD , – –IR0 Decrements the content of
IR0 by 2 and then loads the
bit at that PLC memory
address.
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
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