104
Overview of I/O Memory Area
Section 4-1
4-1
Overview of I/O Memory Area
4-1-1
I/O Memory Area
This region of memory contains the data areas that can be accessed as
instruction operands. I/O memory includes the CIO Area, Work Area, Holding
Area, Auxiliary Area, DM Area, Timer Area, Counter Area, Task Flag Area,
Data Registers, Index Registers, Condition Flag Area, and Clock Pulse Area.
Note
1.
A0 to A447 are read only and cannot be written. A448 to A959 are
read/write.
2.
Bits can be manipulated using TST(350), TSTN(351), SET, SETB(532),
RSTB(533), and OUTB(534).
Instruction
I/O Memory
Area
Size
Range
Task usage
Allocation
Bit
access
Word
access
Access
Change
from CX-
Programmer
Forcing
bit
status
Read
Write
CIO
Area
I/O Area
Input
Area
1,600 bits
(100
words)
CIO 0 to
CIO 99
Shared by
all tasks
CP1L-EL/EM
CPU Units and
CP-series
Expansion
Units or
Expansion I/O
Units
OK
OK
OK
OK
OK
OK
Output
Area
1,600 bits
(100
words)
CIO 100
to CIO
199
OK
OK
OK
OK
OK
OK
1:1 Link Area
256 bits
(16 words)
CIO 3000
to CIO
3015
1:1 Links
OK
OK
OK
OK
OK
OK
Serial PLC Link Area
1,440 bits
(90 words)
CIO 3100
to CIO
3189
Serial PLC
Links
OK
OK
OK
OK
OK
OK
Work Area
14,400
bits (900
words)
CIO 3800
to CIO
6143
---
OK
OK
OK
OK
OK
OK
Work Area
8,192 bits
(512
words)
W000 to
W511
---
OK
OK
OK
OK
OK
OK
Holding Area
8,192 bits
(512
words)
H000 to
H511
(Note 6)
---
OK
OK
OK
OK
OK
OK
Auxiliary Area
15,360
bits (960
words)
A000 to
A959
---
OK
---
OK
Note 1
Note 1
No
TR Area
16 bits
TR0 to
TR15
---
OK
OK
OK
OK
No
No
Data Memory Area
32,768
words
D00000
to
D32767
(Note 7)
---
No
(Note
2)
OK
OK
OK
OK
No
Timer Completion Flags
4,096 bits
T0000 to
T4095
---
OK
---
OK
OK
OK
OK
Counter Completion Flags
4,096 bits
C0000 to
C4095
---
OK
---
OK
OK
OK
OK
Timer PVs
4,096
words
T0000 to
T4095
---
---
OK
OK
OK
OK
No
(Note 4)
Counter PVs
4,096
words
C0000 to
C4095
---
---
OK
OK
OK
OK
No
(Note 5)
Task Flag Area
32 bits
TK0 to
TK31
---
OK
---
OK
No
No
No
Index Registers
16 regis-
ters
IR0 to
IR15
Function
separately
in each task
(Note 3)
---
OK
OK
Indirect
address-
ing only
Specific
instruc-
tions only
No
No
Data Registers
16 regis-
ters
DR0 to
DR15
---
No
OK
OK
OK
No
No
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......