Omron CP1L-EL20DR-D, Operation Manual

Page: 817 / 856

783
PLC Setup Appendix G
2 2-1 2-1-3 Unit Num-
ber 0 0 Every cycle 147
(CP1L
EM-type
CPU Unit) 00 to
07 00 hex
: :
31 161
(CP1L EL-
type CPU
Unit) 1F hex
2-2 NT Link (1:N): 1:N NT Links
2-2-1 Baud 9,600
(disabled) 38,400 (standard) Every cycle 145
(CP1L
EM-type
CPU Unit) 00 to
07 00 hex
115,200 (high speed) 0A hex
161
(CP1L EL-
type CPU
Unit)
2-2-2 NT/PC
Link Max:
Highest
unit num-
ber 0 0 Every cycle 150
(CP1L
EM-type
CPU Unit) 00 to
03 0 hex
: :
7 166
(CP1L EL-
type CPU
Unit) 7 hex
2-3 RS-232C
2-3-1 Baud 9600 bps 300 bps Every cycle 145
(CP1L
EM-type
CPU Unit) 00 to
07 01 hex
600 bps 02 hex
1,200 bps 03 hex
2,400 bps 161
(CP1L EL-
type CPU
Unit) 04 hex
4,800 bps 05 hex
9,600 bps 00 or
06 hex
19,200 bps 07 hex
38,400 bps 08 hex
57,600 bps 09 hex
115,200 bps 0A hex
2-3-2 Format
(data
length,
stop bits,
parity) 7,2,E: 7-bit
data, 2 stop
bits, even parity 7,2,E: 7-bit data, 2 stop
bits, even parity Every cycle 144
(CP1L
EM-type
CPU Unit) 00 to
03 0 hex
7,2,O: 7-bit data, 2 stop
bits, odd parity 1 hex
7,2,N: 7-bit data, 2 stop
bits, no parity 2 hex
7,1,E: 7-bit data, 2 stop
bits, even parity 160
(CP1L EL-
type CPU
Unit) 4 hex
7,1,O: 7-bit data, 1 stop
bit, odd parity 5 hex
7,1,N: 7-bit data, 1 stop
bit, no parity 6 hex
8,2,E: 8-bit data, 2 stop
bits, even parity 8 hex
8,2,O: 8-bit data, 2 stop
bits, odd parity 9 hex
8,2,N: 8-bit data, 2 stop
bits, no parity A hex
8,1,E: 8-bit data, 1 stop
bit, even parity C hex
8,1,O: 8-bit data, 1 stop
bit, odd parity D hex
8,1,N: 8-bit data, 1 stop
bit, no parity E hex
Name Default Settings When setting is read
by CPU Unit
Internal
address
Bits Settings