125
Index Registers
Section 4-11
(2) If two-word data is accessed from the last address in the DM Area (D9999
for the CP1L-EL20D
@
-
@
and D32767 for other CPU Units), the Access
Error Flag (P_AER) will turn ON and the data at D9999 or D32767 will not
be read or written.
DM Fixed Allocation
Words for Modbus-RTU
Easy Master
The following DM area words are used as command and response storage
areas for the Modbus-RTU Easy Master function.
D32200 to D32299: Serial port 1 on CP1L CPU Unit with EM CPU type
D32300 to D32399: Serial port 2 on CP1L CPU Unit with EM CPU type and
serial port 1 on CP1L CPU Unit with EL CPU type
For use of these areas, refer to 8-3-3 Modbus-RTU Easy Master Function.
4-11 Index Registers
The sixteen Index Registers (IR0 to IR15) are used for indirect addressing.
Each Index Register can hold a single PLC memory address, which is the
absolute memory address of a word in I/O memory. Use MOVR(560) to con-
vert a regular data area address to its equivalent PLC memory address and
write that value to the specified Index Register. (Use MOVRW(561) to set the
PLC memory address of a timer/counter PV in an Index Register.)
Note
Refer to Appendix E Memory Map for more details on PLC memory
addresses.
Indirect Addressing
When an Index Register is used as an operand with a “,” prefix, the instruction
will operate on the word indicated by the PLC memory address in the Index
Register, not the Index Register itself. Basically, the Index Registers are I/O
memory pointers.
• All addresses in I/O memory (except Index Registers, Data Registers,
and Condition Flags) can be specified seamlessly with PLC memory
addresses. It isn’t necessary to specify the data area. I/O memory
addresses for IR, DR, and Condition Flags, however, cannot be held.
• In addition to basic indirect addressing, the PLC memory address in an
Index Register can be offset with a constant or Data Register, auto-incre-
mented, or auto-decremented. These functions can be used in loops to
read or write data while incrementing or decrementing the address by one
each time that the instruction is executed.
With the offset and increment/decrement variations, the Index Registers can
be set to base values with MOVR(560) or MOVRW(561) and then modified as
pointers in each instruction.
Note
(1) It is possible to specify regions outside of I/O memory and generate an
Illegal Access Error when indirectly addressing memory with Index Reg-
isters. Refer to Appendix E Memory Map for details on the limits of PLC
memory addresses.
I/O Memory
Pointer
Set to a base value
with MOVR(560) or
MOVRW(561).
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......