155
Trial Operation and Debugging
Section 5-3
Related Auxiliary Bits/Words
5-3-4
Tracing Data
The Data Trace function samples specified I/O memory data using any one of
the following timing methods. It stores the sampled data in Trace Memory,
where they can be read and checked later from the CX-Programmer.
• Specified sampling time (10 to 2,550 ms in 10-ms units)
• One sample per cycle
• When the TRACE MEMORY SAMPLING instruction (TRSM(045)) is exe-
cuted
Up to 31 bits and 6 words in I/O memory can be specified for sampling.
Basic Procedure
1,2,3...
1.
Sampling will start when the parameters have been set from the CX-Pro-
grammer and the command to start tracing has been executed.
2.
Sampled data (after step 1 above) will be traced when the trace trigger
condition is met, and the data just after the delay (see note 1) will be stored
in Trace Memory.
3.
Memory data will be sampled until the Trace Memory is full, and then the
trace will be ended.
Note
Delay value: Specifies how many sampling periods to offset the sampling in
Trace Memory from when the trace condition is met. The setting ranges are
shown in the following table.
Positive delay: Store data delayed by the set delay.
Negative delay: Store previous data according go to the set delay.
Example:
Sampling at 10 ms with a –30 ms delay time yields –30 × 10 =
300 ms, so data 300 ms before the trigger will be stored.
Name
Address
Description
Online Edit Disable Bit Validator
A527.00 to
A527.07
Enables using the Online Edit Disable Bit (A527.09).
Not 5A: Online Edit Disable Bit disabled.
5A:
Online Edit Disable Bit enabled.
Online Edit Disable Bit
A527.09
To disable online editing, set the Online Edit Disable Bit Validator
(A527.00 to A527.07) to 5A and turn ON this bit ON.
Online Editing Wait Flag
A201.10
ON while an online editing process is on standby because online editing
is disabled.
Online Editing Processing Flag
A201.11
ON while an online editing process is being executed.
No. of words
sampled
Setting range
0
–1999 to 2000
1
–1332 to 1333
2
–999 to 1000
3
–799 to 800
4
–665 to 666
5
–570 to 571
6
–499 to 500
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......