28
Specifications
Section 2-2
Characteristics
Type
EM CPU Units
EL CPU Units
Model
CP1L-EM40DR-D
CP1L-EM40DT-D
CP1L-EM40DT1-D
CP1L-EM30DR-D
CP1L-EM30DT-D
CP1L-EM30DT1-D
CP1L-EL20DR-D
CP1L-EL20DT-D
CP1L-EL20DT1-D
Program capacity
(See note 1.)
10 K steps
5 K steps
FB capacity
10 K steps
Control method
Stored program method
I/O control method
Cyclic scan with immediate refreshing
Program
language
Ladder diagram
Function blocks
Maximum number of function block definitions: 128
Maximum number of instances: 256
Languages usable in function block definitions: Ladder diagrams, structured text (ST)
Instruction length
1 to 7 steps per instruction
Instructions
Approx. 500 (function codes: 3 digits)
Instruction
execution time
Basic instructions: 0.61
μ
s min.
Special instructions: 4.1
μ
s min.
Common
processing time
0.38 ms
Number of
connectable Expan-
sion Units and Expan-
sion I/O Units
3 Units (CP Series)
1 Unit (CP Series)
Maximum number of
I/O points
160 points
(40 built in, 40
×
3 expansion)
150 points
(30 built in, 40
×
3 expansion)
60 points
(20 built in, 40
×
1 expansion)
Built-in
terminals
(Func-
tions can
be
assigned.)
Built-in I/O
40 terminals
(24 inputs and 16 outputs)
30 terminals
(18 inputs and 12 outputs)
20 terminals
(12 inputs and 8 outputs)
Inter-
rupt
inputs
Direct
mode
6 inputs
Response time: 0.3 ms
Counter
mode
6 inputs
Response frequency: 5 kHz total, 16 bits
Incrementing counter or decrementing counter
Quick-
response
inputs
6 points
Min. input pulse width: 50
μ
s max.
High-speed
counters
4 inputs/2 axes (24 VDC)
• Single phase (pulse plus direction, up/down, increment), 100 kHz
• Differential phases (4
×
), 50 kHz
Value range: 32 bits, Linear mode or ring mode
Interrupts: Target value comparison or range comparison
Pulse
outputs
(Tran-
sistor
output
models
only)
Pulse outputs
2 outputs, 1 Hz to 100 kHz
(CCW/CW or pulse plus direction)
Trapezoidal or S-curve acceleration and deceleration (Duty ratio: 50% fixed)
PWM outputs
2 outputs, 0.1 to 6,553.5 Hz or 1 to 32,800 Hz
Variable duty ratio: 0.0% to 100.0% (in increments of 0.1% or 1%)
Accuracy: +1%/-0% at 0.1 Hz to 10,000 Hz and +5%/-0% at 10,000 Hz to 32,800 Hz
Built-in analog input
2 inputs (Resolution: 1/1000, Input range: 0 to 10 V)
Ethernet port
Supported. (1 Ethernet port built-in)
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......