Motorola MPC8260 PowerQUICC II, User Manual

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12-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Figure 12-1. Test Logic Block Diagram
The TAP consists of the signals in Table 12-1.
12.2 TAP Controller
The TAP controller is responsible for interpreting the sequence of logical values on the
TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic.
The value shown adjacent to each bubble represents the value of the TMS signal sampled
on the rising edge of the TCK signal. Figure 12-2 shows the state machine.
Table 12-1. TAP Signals
Signal Description
TCK A test clock input to synchronize the test logic.
TMS A test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of TCK to
sequence the TAP controllerÕs state machine.
TDI A test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK.
TDO A data output that can be three-stated and actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCK.
TRST An asynchronous reset with an internal pull-up resistor that provides initialization of the TAP controller and
other logic required by the standard.
Boundary Scan Register
Bypass
M
U
X
Instruction Apply & Decode Register
4ÐBit Instruction Register
M
U
X
TDO
TDI
TMS
TCK
TRST
0 1 2
TAP Controller
3