Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 10. Memory Controller 10-67
Part III. The Hardware Interface
3. Program MPTPR and L/PSRT if refresh is required.
4. Program the machine mode register (M
x MR).
Patterns are written to the RAM array by setting M x MR[OP] = 01 and accessing the UPM
with a single byte transaction. See Figure 10-11.
10.6.3 Clock Timing
Fields in the RAM word specify the value of the various external signals at each clock edge.
The signal timing generator causes external signals to behave according to the timing
speciÞed in the current RAM word. Figure 10-58 and Figure 10-59 show the clock schemes
of the UPMs in the memory controller for integer and non-integer clock ratios. The clock
phases shown reßect timing windows during which generated signals can change state. If
speciÞed in the RAM, the value of the external signals can be changed after any of the
positive edges of T[1Ð4], plus a circuit delay time as speciÞed in the
MPC8260 Hardware
SpeciÞcations .
Note that for integer clock ratios, the widths of T1/2/3/4 are equal, for a 1:2.5 clock ratio,
T1 = 4/3*T2 and T3 = 4/3*T4, and for a 1:3.5 clock ratio, the ticks widths are T1 = 3/2*T2
and T3 = 3/2*T4.
Figure 10-58. Memory Controller UPM Clock Scheme for Integer Clock Ratios
CLKIN
T1
T2
T3
T4