Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 13. Communications Processor Module Overview 13-19
Part IV. Communications Processor Module
timer tables. These timers are clocked from an internal timer that only the CP uses. The
following is a list of the RISC timer tables important features.
¥ Supports up to 16 timers.
¥ Two timer modes: one-shot and restart.
¥ Maskable interrupt on timer expiration.
¥ Programmable timer resolution as Þne as 7.7µs at 133 MHz (6.17 µs at 166 MHz).
¥ Maximum timeout period of 31.8 seconds at 133 MHz (25.5 seconds at 166 MHz).
¥ Continuously updated reference counter.
All operations on the RISC timer tables are based on a fundamental tick of the CPÕs internal
timer that is programmed in the RCCR. The tick is a multiple of 1,024 general system
clocks; see Section 13.3.6, ÒRISC Controller ConÞguration Register (RCCR).Ó
The RISC timer tables have the lowest priority of all CP operations. Therefore, if the CP is
so busy with other tasks that it does not have time to service the timer during a tick interval,
one or more timer may not be updated accurately. This behavior can be used to estimate the
worst-case loading of the CP; see Section 13.6.10, ÒUsing the RISC Timers to Track CP
Loading.Ó
The timer table is conÞgured using the RCCR, the timer table parameter RAM, and the
RISC controller timer event/mask registers (RTER/RTMR), and by issuing
SET TIMER
to
the CPCR.
13.6.1 RISC Timer Table Parameter RAM
Two areas of dual-port RAM, shown in Figure 13-9, are used for the RISC timer tables:
¥ The RISC timer table parameter RAM
¥ The RISC timer table entries
Figure 13-9. RISC Timer Table RAM Usage
TM_BASE
16 RISC
Timer Table
Entries
(Up to 64 Bytes)
RISC
Timer Table
Parameter RAM
0x8AE0
Timer Table Base Pointer