Motorola MPC8260 PowerQUICC II, User Manual

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28-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
The BDs and data buffers can be anywhere in the system memory.
The CP processes the TxBDs in a straightforward fashion. Once the transmit side of an FCC
is enabled, it starts with the Þrst BD in that FCCÕs TxBD table. When the CP detects that
TxBD[R] is set, it begins processing the buffer. The CP detects that the BD is ready either
by polling the R bit periodically or by the user writing to the TODR. When the data from
the BD has been placed in the transmit FIFO buffer, the CP moves on to the next BD, again
waiting for the R bit to be set. Thus, the CP does no look-ahead BD processing, nor does it
skip over BDs that are not ready. When the CP sees the wrap (W) bit set in a BD, it goes
back to the beginning of the BD table after processing of the BD is complete.
After using a BD, the CP normally clears R (not-ready); thus, the CP does not use a BD
again until the BD has been prepared by the core. Some protocols support continuous
mode, which allows repeated transmission and for which the R bit remains set (always
ready).
The CP uses RxBDs in a similar fashion. Once the receive side of an FCC is enabled, it
starts with the Þrst BD in the FCCÕs RxBD table. Once data arrives from the serial line into
the FCC, the CP performs the required protocol processing on the data and moves the
resultant data to the buffer pointed to by the Þrst BD. Use of a BD is complete when no
room is left in the buffer or when certain events occur, such as the detection of an error or
end-of-frame. Regardless of the reason, the buffer is then said to be closed and additional
data is stored using the next BD. Whenever the CP needs to begin using a BD because new
data is arriving, it checks the E bit of that BD. This check is made on a prefetched copy of
the current BD. If the current BD is not empty, it reports a busy error. However, it does not
move from the current BD until it is empty. Because there is a periodic prefetch of the
RxBD, the busy error may recur if the BD is not prepared soon enough.
When the CP sees the W bit set in a BD, it returns to the beginning of the BD table after
processing of the BD is complete. After using a BD, the CP clears the E bit (not empty) and
does not use a BD again until the BD has been processed by the core. However, in
continuous mode, available to some protocols, the E bit remains set (always empty).
28.7 FCC Parameter RAM
Each FCC parameter RAM area begins at the same offset from each FCC base area. The
protocol-speciÞc portions of the FCC parameter RAM are discussed in the speciÞc protocol
descriptions. Table 28-5 shows portions common to all FCC protocols.