Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-15
Part IV. Communications Processor Module
Data length represents the number of octets the CP writes into the buffer. After data is
received in buffer, the CP only writes them once as the BD closes. Note that
the
memory
allocated for this buffer should be no smaller than MRBLR. The Rx data buffer pointer
points to the Þrst location of the buffer and must be even. The buffer can be in internal or
external memory. Figure 26-7 shows the UART RxBD process, showing RxBDs after they
receive 10 characters, an idle period, and Þve characters (one with a framing error). The
example assumes that MRBLR = 8.
4Ð5 Ñ Reserved, should be cleared.
6 CM Continuous mode.
0 Normal operation.
1 The CP does not clear the E bit after this BD is closed, allowing the CP to automatically overwrite
the buffer when it next accesses the BD. However, E is cleared if an error occurs during reception,
regardless of how CM is set.
7 ID Buffer closed on reception of idles. Set when the buffer has closed because a programmable number
of consecutive idle sequences is received. The CP writes ID after received data is in the buffer.
8Ð9 Ñ Reserved, should be cleared.
10 BR Buffer closed on reception of break. Set when the buffer closes because a break sequence was
received. The CP writes BR after the received data is in the buffer.
11 FR Framing error. Set when a character with a framing error is received and located in the last byte of this
buffer. A framing error is a character with no stop bit. A new receive buffer is used to receive additional
data. The CP writes FR after the received data is in the buffer.
12 PR Parity error. Set when a character with a parity error is received in the last byte of the buffer. A new
buffer is used for additional data. The CP writes PR after received data is in the buffer.
13 Ñ Reserved, should be cleared.
14 OV Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received
data is in the buffer.
15 Ñ Reserved, should be cleared.
Table 26-7. SMC UART RxBD Field Descriptions (Continued)
Bit Name Description