MOTOROLA
Chapter 26. Serial Management Controllers (SMCs)
26-17
Part IV. Communications Processor Module
Table 26-8 describes SMC UART TxBD Þelds.
Data length represents the number of octets that the CP should transmit from this BD data
buffer. However, it is never modiÞed by the CP and normally is greater than zero. It can be
zero if P is set and only a preamble is sent. If there are more than 8 bits in the UART
character, data length should be even. For example, to transmit three UART characters of
8-bit data, 1 start, and 1 stop, initialize the data length Þeld to 3. To send three UART
characters of 9-bit data, 1 start, and 1 stop, the data length Þeld should 6, because the three
9-bit data Þelds occupy three half words in memory (the 9 least-signiÞcant bits of each half
word).
Tx data buffer pointer points to the Þrst location of the buffer. It can be even or odd, unless
the number of data bits in the UART character is greater than 8 bits. Then the buffer pointer
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
R
Ñ
W
I
Ñ
CM
P
Ñ
2
Data Length
4
Tx Data Buffer Pointer
6
Figure 26-8. SMC UART TxBD
Table 26-8. SMC UART TxBD Field Descriptions
Bits
Name
Description
0
R
Ready
0 The buffer is not ready for transmission; BD and its buffer can be altered. The CP clears R after the
buffer has been sent or an error occurs.
1 The buffer has not been completely sent. This BD cannot updated while R is set.
1
Ñ
Reserved, should be cleared.
2
W
Wrap (Þnal BD in the TxBD table)
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that
TBASE points to. The number of TxBDs in this table is determined only by the W bit and overall
space constraints of the dual-port RAM.
3
I
Interrupt
0 No interrupt is generated after this buffer is serviced.
1 The SMCE[TXB] is set when this buffer is serviced. TXB can cause an interrupt if it is enabled.
4Ð5
Ñ
Reserved, should be cleared.
6
CM
Continuous mode
0 Normal operation.
1 The CP does not clear R after this BD is closed and automatically retransmits the buffer when it
accesses this BD next.
7
P
Preamble
0 No preamble sequence is sent.
1 The UART sends one all-ones character before it sends the data so that the other end detects an
idle line before the data is received. If this bit is set and the data length of this BD is zero, only a
preamble is sent.
8Ð15 Ñ
Reserved, should be cleared.
Summary of Contents for MPC8260 PowerQUICC II
Page 1: ...MPC8260UM D 4 1999 Rev 0 MPC8260 PowerQUICC II UserÕs Manual ª ª ...
Page 66: ...lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA ...
Page 88: ...1 18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Page 120: ...2 32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Page 138: ...Part II iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II Configuration and Reset ...
Page 184: ...4 46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II ConÞguration and Reset ...
Page 202: ...Part III vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 266: ...8 34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 382: ...10 106 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 392: ...11 10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Page 430: ...Part IV viii MOTOROLA Part IV Communications Processor Module ...
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Page 980: ...A 4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Appendixes ...
Page 1002: ...Index 22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA INDEX ...
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