Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-17
Part IV. Communications Processor Module
0x0E STS Hword Source transfer size in bytes. All transfers from the source (except the start
alignment and the end) are written to the bus using this parameter.
In memory-to-peripheral mode, STS should be initialized to SS_MAX.
In peripheral-to-memory mode, STS should be initialized to the peripheral port
size or peripheral transfer size (if the peripheral accepts bursts). See Table 18-8
for valid STS values for peripherals.
In ßy-by mode, STS is initialized to the peripheral port size.
In memory-to-memory mode:
¥ STS should be initialized to SS_MAX.
¥ DTS value should be initialized to SS_MAX. STS can be initialized to values
other than SS_MAX in the following conditions:
ÐSTS must divide SS_MAX.
ÐSTS must be divided by 32 to enable bursts during the steady-state phase.
See Table 18-7 for memory-to-memory valid STS values.
0x10 DPR_OUT_PTR Hword Read pointer inside the internal buffer.
0x12 SEOB Hword Source end of burst. Used for alignment of the Þrst read burst.
0x14 DEOB Hword Destination end of burst. Used for alignment of the Þrst write burst.
0x16 DTS Hword Destination transfer size in bytes. All transfers to destination (except the start
alignment and the tail) are written to the bus using this parameter.
In peripheral-to-memory mode, DTS should equal SS_MAX.
In memory-to-peripheral modes, initialize DTS to the peripheral port size if
transferÕs destination is a peripheral. Valid sizes for peripheral destination is 1, 2,
4, and 8 bytes, or peripheral transfer size (if the peripheral accepts bursts). See
Table 18-8 for valid STS values for peripherals.
In ßy-by mode, DTS is initialized to the peripheral port size.
In memory-to-memory mode:
¥
DTS value is initialized to SS_MAX.
¥ STS value is initialized to SS_MAX. DTS can be initialized to values other
than SS_MAX in the following conditions:
ÐDTS must divide SS_MAX.
ÐDTS must be divided by 32, to enable bursts in steady-state phase.
See Table 18-8 for valid memory-to-memory DTS values.
0x18 RET_ADD Hword Used to save return address when working in ERM = 1 mode.
0x1A Ñ Hword Reserved, should be cleared.
0x1C BD_CNT Word Internal byte count.
0x20 S_PTR Word Source internal data pointer.
0x24 D_PTR Word Destination internal data pointer.
0x28 ISTATE Word Internal. Should be cleared before every
START
_
IDMA
command.
1
From the pointer value programmed in IDMA x _BASE: IDMA1_BASE at 0x87FE, IDMA2_BASE at 0x88FE,
IDMA3_BASE at 0x89FE, and IDMA4_BASE at 0x8AFE; see Section 13.5.2, ÒParameter RAM.Ó
Table 18-4. IDMA x Parameter RAM (Continued)
Offset
1
Name Width Description