Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 9. Clocks and Power Control 9-7
Part III. The Hardware Interface
9.6.1 General System Clocks
The general system clocks (CPM_CLK, CPM_CLK_90) are the basic clocks supplied to
most modules and sub-modules on the CPM. The following points should be kept in mind:
¥ BUS_CLK and BUS_CLK_90 are supplied to the 60x bus and to the core.
¥ Many modules use both clocks (SIU, serials)
¥ The external clock, CLKIN, is the same as BUS_CLK
9.7 PLL Pins
Table 9-3 shows dedicated PLL pins.
Figure 9-2 shows the Þltering circuit for VCCSYN and VCCSYN1, described in Table 9-3.
Table 9-3. Dedicated PLL Pins
Signal Description
VCCSYN1 Drain voltageÑAnalog VDD dedicated to core analog PLL circuits. To ensure core clock stability, Þlter the
power to the VCCSYN1 input with a circuit similar to the one in Figure 9-2. To Þlter as much noise as
possible, place the circuit as close as possible to VCCSYN1. The 0.1-µF capacitor should be closest to
VCCSYN1, followed by the 10-µF capacitor, and Þnally the 10-
W
resistor to Vdd. These traces should be
kept short and direct.
VCCSYN Drain voltageÑAnalog VDD dedicated to analog main PLL circuits. To ensure internal clock stability, Þlter
the power to the VCCSYN input with a circuit similar to the one in Figure 9-2. To Þlter as much noise as
possible, place the circuit should as close as possible to VCCSYN. The 0.1-µF capacitor should be closest
to VCCSYN, followed by the 10-µF capacitor, and Þnally the 10-
W
resistor to Vdd. These traces should be
kept short and direct.
GNDSYN Source voltageÑAnalog VSS dedicated to analog main PLL circuits. Should be provided with an extremely
low impedance path to ground and should be bypassed to VCCSYN by a 0.1-µF capacitor located as close
as possible to the chip package. The user should also bypass GNDSYN to VCCSYN with a 0.01-µF
capacitor as close as possible to the chip package.
XFC External Þlter capacitorÑConnects to the off-chip capacitor for the main PLL Þlter. One terminal of the
capacitor is connected to XFC while the other terminal is connected to VCCSYN.
30 M
W
is the minimum parasitic resistance value that ensures proper PLL operation when connected in
parallel with the XFC capacitor. XFC capacitor values are shown in the table below:
Multiplication
Factor
2 Volts (Minimum) 2.5 Volts (Maximum) Unit
1
£
Factor
£
4 XFC = Factor * 935- 90 XFC = Factor * 680 - 90 pF
Factor > 4 XFC = Factor * 1370 XFC = Factor * 970 pF
Note that the multiplication factor ranges between 1 and 4,096. See the PLLMF Þeld
description in Section 9.9, ÒSystem Clock Mode Register (SCMR).Ó