Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 17. Timers 17-5
Part IV. Communications Processor Module
The TGCR2 register is shown in Figure 17-4.
Table 17-2 describes TGCR2 Þelds.
3 RST2 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if the STP bit is cleared.
4 GM1 Gate mode for TGATE1. This bit is valid only if the gate function is enabled in TMR1 or TMR2.
0 Restart gate mode. TGATE1 is used to enable/disable count. A falling TGATE1 enables and
restarts the count and a rising edge of TGATE1 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not
restart the count value in TCN.
5 Ñ Reserved, should be cleared.
6 STP1 Stop timer.
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock
from the internal bus interface, which allows the user to read and write timer registers. The clocks
to the timer remain stopped until the user clears this bit or a hardware reset occurs.
7 RST1 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if STP = 0.
Bits 0 1 2 3 4 5 6 7
Field CAS4 Ñ STP4 RST4 GM2 Ñ STP3 RST3
Reset 0000_0000
R/W R/W
Addr 0x10D84
Figure 17-4. Timer Global Configuration Register 2 (TGCR2)
Table 17-2. TGCR2 Field Descriptions
Bit Name Description
0 CAS4 Cascade timers.
0 Normal operation.
1 Timers 3 and 4 cascades to form a 32-bit timer.
1 Ñ Reserved, should be cleared.
2 STP 4 Stop timer.
0 Normal operation.
1 Reduce power consumption of the timer. This bit stops all clocks to the timer, except the clock
from the internal bus interface, which allows the user to read and write timer registers. The clocks
to the timer remain stopped until the user clears this bit or a hardware reset occurs.
3 RST4 Reset timer.
0 Reset the corresponding timer (a software reset is identical to an external reset).
1 Enable the corresponding timer if the STP bit is cleared.
Table 17-1. TGCR1 Field Descriptions (Continued)
Bits Name Description