Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 2. PowerPC Processor Core 2-13
Part I. Overview
11 DPM Dynamic power management enable.
1
0 Dynamic power management is disabled.
1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect
operational performance and is transparent to software or any external hardware.
12Ð14 Ñ Reserved
15 NHR Not hard reset (software-use only)ÑHelps software distinguish a hard reset from a soft reset.
0 A hard reset occurred if software had previously set this bit.
1 A hard reset has not occurred. If software sets this bit after a hard reset, when a reset occurs
and this bit remains set, software can tell it was a soft reset.
16 ICE Instruction cache enable
2
0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were
marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and
cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits
are ignored and all accesses are propagated to the bus as single-beat transactions. For those
transactions, however, CI reßects the original state determined by address translation
regardless of cache disabled status. ICE is zero at power-up.
1 The instruction cache is enabled
17 DCE Data cache enable
2
0 The data cache is neither accessed nor updated. All pages are accessed as if they were
marked cache-inhibited (WIM = X1X). Potential cache accesses from the bus (snoop and
cache operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits
are ignored and all accesses are propagated to the bus as single-beat transactions. For those
transactions, however, CI reßects the original state determined by address translation
regardless of cache disabled status. DCE is zero at power-up.
1 The data cache is enabled.
18 ILOCK Instruction cache lock
0 Normal operation
1 Instruction cache is locked. A locked cache supplies data normally on a hit, but an access is
treated as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is
single-beat, however, CI still reßects the original state as determined by address translation
independent of cache locked or disabled status.
To prevent locking during a cache access, an isync must precede the setting of ILOCK.
19 DLOCK Data cache lock
0 Normal operation
1 Data cache is locked. A locked cache supplies data normally on a hit but an access is treated
as a cache-inhibited transaction on a miss. On a miss, the transaction to the bus is single-
beat, however, CI still reßects the original state as determined by address translation
independent of cache locked or disabled status. A snoop hit to a locked L1 data cache
performs as if the cache were not locked. A cache block invalidated by a snoop remains invalid
until the cache is unlocked.
To prevent locking during a cache access, a sync must precede the setting of DLOCK.
Table 2-1. HID0 Field Descriptions (Continued)
Bits Name Description