Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 1. Overview 1-5
Part I. Overview
Figure 1-1. MPC8260 Block Diagram
Both the system core and the CPM have an internal PLL, which allows independent
optimization of the frequencies at which they run. The system core and CPM are both
connected to the 60x bus.
1.2.1 MPC603e Core
The MPC603e core is derived from the PowerPC MPC603e microprocessor without the
ßoating-point unit and with power management modiÞcations. The core is a high-
performance low-power implementation of the PowerPC family of reduced instruction set
computer (RISC) microprocessors. The MPC603e core implements the 32-bit portion of
the PowerPC architecture, which provides 32-bit effective addresses, integer data types of
8, 16, and 32 bits. The MPC603e cache provides snooping to ensure data coherency with
other masters. This helps ensure coherency between the CPM and system core.
The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-
bit split-transaction external data bus, which is connected directly to the external MPC8260
pins.
MPC603e
PowerPC
Core
16-Kbyte
Instruction Cache
IMMU
16-Kbyte
Data Cache
DMMU
60x Bus
Local
Bus
60x -to-Local Bus Bridge
Memory Controller
Bus Interface Unit
Clock Counter
System Functions
Timers
Parallel I/O
Baud Rate Gen.
Interrupt
Controller
24-Kbyte Dual
Port RAM
32-Bit RISC Communications
Processor (CP) and
Serial DMAs
4 Virtual
IDMAs
MCC MCC FCC FCC FCC SCC SCC SCC SCC SMC SMC
SPI
I
2
C
Time Slot Assigner
Serial Interface
8 TDMs 2 UTOPIA 3 MIIs Non-Multiplexed I/O
Program ROM