Motorola MPC8260 PowerQUICC II, User Manual

Page: 313 / 1006

MOTOROLA Chapter 10. Memory Controller 10-37
Part III. The Hardware Interface
The following two methods are used for internal bank interleaving:
¥ Page-based interleavingÑPage-based interleaving yields the best performance and
is the preferred interleaving method. This method uses low address bits as the
Bank-Select for the SDRAM, thus allowing interleaving on every page boundary. It
is activated by setting xSDMR[PBI]=1. See Ò0xSDRAM ConÞguration Example
(Page-Based Interleaving)Ó.
¥ Bank-based interleaving ÑThis method uses the most-signiÞcant address bits as the
bank-select for the SDRAM, thus allowing interleaving only on bank boundaries. It
is activated by clearing xSDMR[PBI]. See Section 10.4.12, ÒSDRAM
ConÞguration Examples.Ó
10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA)
In single MPC8260 mode, the lower bits of the address bus are connected to the deviceÕs
address port, and the memory controller multiplex the row/column and the internal banks
select lines, according to the PL/SDMR[SDAM] and PL/SDMR[BSMA].
Table 10-37 shows how P/LSDMR[SDAM] settings affect address multiplexing. For the
effect of PL/SDMR[BSMA] see Section 10.4.12, ÒSDRAM ConÞguration Examples.Ó
Note that in 60x-compatible mode, the 60x address must be latched and multiplexed by
glue logic that is controlled by ALE and SDAMUX, however, the user still has to conÞgure
PSDMR[SDAM].
On the local bus, only the lower 18 bits of the address are output. Table 10-19 shows
SDRAM address multiplexing for A0ÐA15.
Table 10-19. SDRAM Address Multiplexing (A0ÐA15)
SDAM
External Bus
Address
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
000
Signal driven
on external
pins when
address
multiplexing
is enabled
Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ A5 A6 A7
001 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ A5 A6
010 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ A5
011 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
100 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ
101 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ