Motorola MPC8260 PowerQUICC II, User Manual

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9-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
The direction selected depends on whether the feedback signal phase lags or leads the
reference signal. The output of the charge pump drives the VCO whose output frequency is
divided and fed back to the phase comparator for comparison with the reference signal,
CLKIN. Ranging between 1 and 4,096, the PLL multiplication factor is held in the system
clock mode register (SCMR[PLLMF]). Also, when the PLL is operating, its output
frequency is twice the CPM frequency. This double frequency is required to generate the
CPM_CLK and CPM_CLK_90 clocks. See the block diagram in Figure 9-1 for details.
On initial system power-up, power-on reset (PORESET) should be asserted by external
logic for 16 input clocks after a valid level is reached on the power supply. Whenever
power-on reset is asserted, SCMR[PLLMF, PLLDF] are programmed by the conÞguration
pins; see Table 9-2. This value then drives the clock block to generate the correct CPM and
bus frequencies.
9.4.2 Skew Elimination
The PLL can tighten synchronous timings by eliminating skew between phases of the
internal clock and the external clock entering the chip (CLOCKIN). Skew elimination is
always active when the PLL is enabled. Disabling the PLL can greatly increase clock skew.
9.5 Clock Dividers
The PLL output is twice the maximum frequency needed for all the clocks. The PLL output
is sent to general-purpose dividers (CPMDF, BUSDF), either of which can divide the
double clock by a programmable number between 1 and 16. The delay is the same for all
dividers independent on the programmable number, so the clocks are synchronized.
The output of each divider has two phases, one shifted 90¡ from the other, as shown in
Table 9-1. Each phase has a 50% duty cycle.
9.6 The MPC8260Õs Internal Clock Signals
The internal logic of the MPC8260 uses the following internal clock lines:
¥ CPM general system clocks (CPM_CLK, CPM_CLK_90)
¥ 60x bus, core bus (BUS_CLK, BUS_CLK_90)
¥ SCC clocks (SCC_CLK, SCC_CLK_90)
¥ Baud-rate generator clock (BRG_CLK)
The PLL synchronizes these clock signals to each other (but does not synchronize to
BRG_CLK).