Motorola MPC8260 PowerQUICC II, User Manual

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8-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
software attempt to align code and data where possible.
8.4.3.6 Effect of Port Size on Data Transfers
The MPC8260 can transfer operands through its 64-bit data port. If the transfer is controlled
by the internal memory controller, the MPC8260 can support 8-, 16-, 32-, and 64-bit data
port sizes. The bus requires that the portion of the data bus used for a transfer to or from a
particular port size be Þxed. A 64-bit port must reside on data bus bits D[0Ð63], a 32-bit
port must reside on bits D[0Ð31], a 16-bit port must reside on bits D[0Ð15], and an 8-bit
port must reside on bits D[0Ð7]. The MPC8260 always tries to transfer the maximum
amount of data on all bus cycles: for a word operation, it always assumes the port is 64 bits
wide when beginning the bus cycle; for burst and extended byte cycles, a 64-bit bus is
assumed.
Figure 8-6 shows the device connections on the data bus. Table 8-8 lists the bytes required
on the data bus for read cycles.
Table 8-7. Unaligned Data Transfer Example (4-Byte Example)
Program Size of
Word (4 bytes)
TSIZ[1Ð3] A[29Ð31]
Data Bus Byte Lanes
D0... ...D31 D32... ...D63
B0 B1 B2 B3 B4 B5 B6 B7
Aligned 1 0 0 0 0 0 A
1
1
A: Byte lane used
A A A Ñ
2
2
Ñ: Byte lane not used
Ñ Ñ Ñ
MisalignedÑ1st access 0 1 1 0 0 1 Ñ A A A Ñ Ñ Ñ Ñ
2nd access 0 0 1 1 0 0 Ñ Ñ Ñ Ñ A Ñ Ñ Ñ
MisalignedÑ1st access 0 1 0 0 1 0 Ñ Ñ A A Ñ Ñ Ñ Ñ
2nd access 0 1 0 1 0 0 Ñ Ñ Ñ Ñ A A Ñ Ñ
MisalignedÑ1st access 0 0 1 0 1 1 Ñ Ñ Ñ A Ñ Ñ Ñ Ñ
2nd access 0 1 1 1 0 0 Ñ Ñ Ñ Ñ A A A Ñ
Aligned 1 0 0 1 0 0 Ñ Ñ Ñ Ñ A A A A
MisalignedÑ1st access 0 1 1 1 0 1 Ñ Ñ Ñ Ñ Ñ A A A
2nd access 0 0 1 0 0 0 A Ñ Ñ Ñ Ñ Ñ Ñ Ñ
MisalignedÑ1st access 0 1 0 1 1 0 Ñ Ñ Ñ Ñ Ñ Ñ A A
2nd access 0 1 0 0 0 0 A A Ñ Ñ Ñ Ñ Ñ Ñ
MisalignedÑ1st access 0 0 1 1 1 1 Ñ Ñ Ñ Ñ Ñ Ñ Ñ A
2nd access 0 1 1 0 0 0 A A A Ñ Ñ Ñ Ñ Ñ