Motorola MPC8260 PowerQUICC II, User Manual

Page: 901 / 1006

MOTOROLA Chapter 30. Fast Ethernet Controller 30-27
Part IV. Communications Processor Module
Table 30-11 describes Ethernet TxBD Þelds.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 R PAD W I L TC DEF HB LC RL RC UN CSL
2 Data length
4 Tx data Buffer Pointer
6
Figure 30-10. Fast Ethernet Transmit Buffer (TxBD)
Table 30-11. Ethernet TxBD Field Definitions
Field Name Description
0 R Ready
0 The buffer associated with this BD is not ready for transmission; the user can manipulate this BD
or its associated buffer. The CP clears R after the buffer has been sent or after an error.
1 The buffer is ready to be sent. The buffer is either waiting or in the process of being sent. The
user cannot change Þelds in this BD or its associated buffer once R = 1.
1 PAD Short frame padding. Valid only when L = 1; otherwise, it is ignored.
0 Do not add PADs to short frames.
1 Add PADs to short frames. PAD bytes are inserted until the length of the transmitted frame equals
the MINFLR. The PAD bytes are stored in a buffer pointed to by PAD_PTR in the parameter RAM.
2 W Wrap (Þnal BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP receives incoming data into the Þrst
BD that TBASE points to in the table. The number of TxBDs in this table is programmable and
determined only by the W bit.
The TxBD table must contain more than one BD in Ethernet mode.
3 I Interrupt
0 No interrupt is generated after this buffer is serviced.
1 FCCE[TXB] or FCCE[TXE] is set after this buffer is serviced. These bits can cause interrupts if
they are enabled.
4 L Last
0 Not the last buffer in the transmit frame.
1 Last buffer in the current transmit frame.
5 TC Tx CRC. Valid only when the L bit is set; otherwise, it is ignored.
0 End transmission immediately after the last data byte.
1 Transmit the CRC sequence after the last data byte.
6 DEF Defer indication. This frame did not have a collision before it was sent but it was sent late because of
deferring.
7 HB Heartbeat. The collision input is not asserted within 40 transmit serial clocks following completion of
transmission. This bit cannot be set unless FPSMR[HBC] = 1. Written by the Ethernet controller after
sending the associated buffer.
8 LC Late collision. A collision occurred after the number of bytes deÞned in FPSMR[LCW] (56 or 64) are
sent. The Ethernet controller terminates the transmission and updates LC after sending the buffer.
9 RL Retransmission limit. The transmitter failed (R 1) attempts to successfully send a message
due to repeated collisions. The Ethernet controller updates RL after sending the buffer.