Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 10. Memory Controller 10-47
Part III. The Hardware Interface
Figure 10-38. Mode Data Bit Settings
10.4.10 SDRAM Refresh
The memory controller supplies auto (CBR) refreshes to SDRAM according to the interval
speciÞed in PSRT or LSRT. This represents the time period required between refreshes. The
value of P/LSRT depends on the speciÞc SDRAM devices used and the operating frequency
of the MPC8260Õs bus. This value should allow for a potential collision between memory
accesses and refresh cycles. The period of the refresh interval must be greater than the
access time to ensure that read and write operations complete successfully.
There are two levels of refresh request priorityÑlow and high. The low priority request is
generated as soon as the refresh timer expires, this request is granted only if no other
requests to the memory controller are pending. If the request is not granted (memory
controller is busy) and the refresh timer expires two more times, the request becomes high
priority and is served when the current memory controller operation Þnishes.
Note that there are two SDRAM refresh timers, one for 60x SDRAM machines and one for
local bus SDRAM machines.
10.4.11 SDRAM Refresh Timing
The memory controller implements bank staggering for the auto refresh function. This
reduces instantaneous current consumption for memory refresh operations.
Once a refresh request is granted the memory controller begins issuing auto-refresh
command to each device associated with the refresh timer, in one clock intervals. After the
last
REFRESH
command is issued, the memory controller waits for the number of clocks
written in the SDRAM machineÕs mode register (RFRC in P/LSDMR). The timing is
shown in Figure 10-39
latency modeÑcan be 1(001), 2(010), or 3(011).
burst length:
4(010) for 16- and 64-bit port sizes
8(011) for 8- and 32-bit port sizes
Bit number 0 1 2 3 4 5 6 7 8 9 10 11 lsb
CL 0 BL