Motorola MPC8260 PowerQUICC II, User Manual

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MOTOROLA Chapter 2. PowerPC Processor Core 2-9
Part I. Overview
environment architecture (OEA), as well as the MPC8260 core implementation-speciÞc
registers. Full descriptions of the basic register set deÞned by the PowerPC architecture are
provided in Chapter 2, ÒPowerPC Register Set,Ó in
The Programming Environments
Manual .
The PowerPC architecture deÞnes register-to-register operations for all arithmetic
instructions. Source data for these instructions is accessed from the on-chip registers or is
provided as an immediate value embedded in the opcode. The three-register instruction
format allows speciÞcation of a target register distinct from the two source registers, thus
preserving the original data for use by other instructions and reducing the number of
instructions required for certain operations. Data is transferred between memory and
registers with explicit load and store instructions only.
Figure 2-2 shows the complete MPC8260 register set and the programming environment to
which each register belongs. This Þgure includes both the PowerPC register set and the
MPC8260-speciÞc registers.
Note that there may be registers common to other PowerPC processors that are not
implemented in the MPC8260Õs processor core. Unsupported SPR values are treated as
follows:
¥ Any mtspr with an invalid SPR executes as a no-op.
¥ Any mfspr with an invalid SPR cause boundedly undeÞned results in the target
register.
Conversely, some SPRs in the processor core may not be implemented in other PowerPC
processors, or may not be implemented in the same way in other PowerPC processors.
2.3.1.1 PowerPC Register Set
The PowerPC UISA registers, shown in Figure 2-2, can be accessed by either user- or
supervisor-level instructions. The general-purpose registers (GPRs) and ßoating-point
registers (FPRs) are accessed through instruction operands. Access to registers can be
explicit (that is, through the use of speciÞc instructions for that purpose such as the
mtspr
and mfspr instructions) or implicit as part of the execution (or side effect) of an instruction.
Some registers are accessed both explicitly and implicitly.
The number to the right of the register name indicates the number that is used in the syntax
of the instruction operands to access the register (for example, the number used to access
the XER is one). For more information on the PowerPC register set, refer to Chapter 2,
ÒPowerPC Register Set,Ó in
The Programming Environments Manual .
Note that the reset value of the MSR exception preÞx bit (MSR[IP]), described in the
MPC603e UserÕs Manual , is determined by the CIP bit in the hard reset conÞguration word
in the MPC8260. This is described in Section 5.4.1, ÒHard Reset ConÞguration Word .Ó