4-18
Performance
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
Table 4-2 shows the timing of internal operations from dis-
patch to retire of each ROP for nearly two iterations of this
loop. All memory accesses are assumed to hit in the cache.
EVEN_ARRAY_SIZE is set to 20.
Table 4-2. Integer Dot Product Internal Operations Timing
Instruction
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MOV EAX,[ESI][ECX*4]
L
>
-
-
-
!
MOV EBX,[ESI][ECX*4]+4
L
>
-
-
-
!
IMUL EAX,[EDI][ECX*4]
L
>
-
-
!
-
M
M
M
M
>
!
IMUL EBX,[EDI][ECX*4]+4
L
>
-
-
-
!
-
M
M
M
M
>
!
ADD ECX,2
A
>
-
-
-
!
ADD EDX,EAX
-
-
-
A
>
!
ADD EBP,EBX
-
-
-
A
>
!
CMP ECX,20
-
-
-
A
>
!
JL LOOP
-
-
-
-
B
>
!
MOV EAX,[ESI][ECX*4]
L
>
-
-
-
!
MOV EBX,[ESI][ECX*4]+4
L
>
-
-
-
!
IMUL EAX,[EDI][ECX*4]
L
>
-
-
!
-
M
M
M
M
>
!
IMUL EAX,[EDI][ECX*4]+4
L
>
-
-
-
!
-
M
M
M
M
>
Notes:
L— load execute
M— multiply execute
A— ALU execute
B— branch execute
>— result
!— retire (update real state)
- — preceding or after execute: waiting in the reservation station
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...