Cache Organization and Management
2-21
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
2.3.6
Snooping
The term snooping commonly refers to at least three different
actions, only two of which are supported by the AMD-K5 and
Pentium processors:
■
Inquire Cycles—These are bus cycles initiated by external
logic that cause the processor to look up an address in its
physical cache tags. Both the AMD-K5 and Pentium proces-
sors support inquire cycles.
■
Internal Snooping—This is initiated by the processor (rather
than external logic) during certain cache accesses. Internal
snooping detects self-modifying code. Both the AMD-K5 and
Pentium processors support internal snooping.
■
Bus Watching—Some caching devices watch their address
and data buses while they are held off the bus, comparing
addresses driven by another bus master with their internal
cache tags and optionally updating their cached lines on the
fly during writebacks by the other master. The AMD-K5 and
the Pentium processor do not support bus watching.
Table 2-4 shows the conditions under which snooping occurs in
the AMD-K5 processor and the resources that are snooped. All
such snooping is done in the processor’s physical tags, in paral-
lel with the processor’s own accesses to the linear tags. Thus,
there is no execution-performance penalty for snooping.
Inquire Cycles
In systems with multiple caching masters, external logic main-
tains cache coherency by driving inquire cycles to the proces-
sor. System logic initiates inquire cycles by asserting AHOLD,
BOFF, or HOLD to obtain control of the address bus, and then
driving EADS, INV and an inquire address. Such bus cycles
cause the processor to compare the physical tags for both its
instruction and data caches with the inquire address. If the
compare hits a shared or exclusive line in the data cache or a
valid line in the instruction cache, the processor asserts HIT. If
the compare hits a modified line in the data cache, the proces-
sor asserts HITM.
The resulting state of a cache line that is hit depends on the
state of the INV signal at the time of the inquire cycle. If INV is
negated, the line remains in or transitions to the shared (or
valid) state. If INV is asserted, the modified line in the data
cache is written back, and the line is invalidated.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...