Bus Cycle Timing
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18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
Locked Operation
with BOFF
Intervention
Unlike AHOLD and HOLD, BOFF does not permit an in-
progress bus cycle to complete. It forces the processor off the
bus in the next clock, aborting any in-progress bus cycle that
the processor may have begun. If BOFF is asserted during a
locked operation, only the cycle(s) aborted before their last
BRDY and the cycles not yet run are restarted after BOFF is
negated. Thus, system logic must keep track of all cycles in the
locked operation that have completed before the assertion of
BOFF and must continue the locked operation immediately
after BOFF is negated, except that if a writeback is pending
when BOFF is negated, the writeback takes precedence over
the restarting of the aborted cycles in the locked operation.
Figure 5-18 shows the effect of BOFF intervening in a locked
read-write pair of bus cycles. The example begins with the
read, while LOCK is asserted. System logic asserts BOFF while
the processor is asserting ADS for the write, causing the pro-
cessor to abort the write and float its bus in the next clock.
Another bus master must wait two clocks after the assertion of
BOFF before driving its first bus cycle, because the processor
does not float its outputs until one clock after the assertion of
BOFF.
When system logic relinquishes the bus by negating BOFF, the
processor almost immediately drives the bus again, with LOCK
asserted, and restarts the aborted write access by asserting
ADS as early as one clock after BOFF is negated.
System logic should ensure that the processor results for inter-
rupted and uninterrupted locked cycles are consistent. That is,
system logic must guarantee that the memory accessed by the
processor is not modified during the time another bus master
controls the bus.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...