Bus Cycle Timing
5-159
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
AHOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
Figure 5-10 shows an example similar to Figure 5-9, minus the
address parity error, but this inquire cycle hits either a shared
or exclusive line in the cache, as indicated by the assertion of
HIT and the negation of HITM two clocks after the assertion of
EADS. The processor invalidates the cache line because sys-
tem logic asserts INV with EADS. The processor may drive a
new bus cycle as early as one clock after system logic negates
AHOLD.
Figure 5-10. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
CLK
A31–A3
ADS
AHOLD
BE7–BE0
BRDY
D/C
D63–D0
EADS
HIT
HITM
INV
M/IO
W/R
CLK
Read
Inquire
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...