Signal Descriptions
5-71
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
Inquire cycle logic in systems with look-through caches, how-
ever, normally monitor both HIT and HITM because such sys-
tems often implement the write-once cache protocol. The
write-once protocol requires caching in the exclusive state at
certain transitions, and the exclusive state can only be identi-
fied if both HIT and HITM are monitored. For details on this
protocol, see Section 6.2.6 on page 6-19.
Inquire cycles can be driven while LOCK is asserted, if
AHOLD is used to obtain the bus for the inquire cycle. An
inquire cycle cannot hit a line that is involved in a locked oper-
ation (LOCK asserted). The processor prevents this by always
checking its cache tags prior to a locked operation. If the loca-
tion is cached, it is written back (if necessary) and invalidated
prior to the locked operation.
The Pentium processor does not recognize an inquire cycle hit
on an in-progress cache line fill prior to the first BRDY, and it
will cache that line in the exclusive state if PWT = 0 and WB/
WT = 1. This may cause the line to be cached in the exclusive
state in two separate caches if the system supports other cach-
ing masters. In such cases, the AMD-K5 processor asserts HIT
and caches the line in the shared state or does not cache it,
depending on the state of the INV signal.
Table 5-11. MESI-State Transitions for Inquire Cycles
Signal or Event
Result of Cache Lookup
Inquire Miss
Inquire Hit
shared or exclusive
modified
HIT
1
0
0
0
0
HITM
1
1
2
1
1
0
0
INV
—
1
0
1
0
Write to Memory
no
no
no
writeback (32
bytes)
writeback (32
bytes)
State After Inquire
3
—
invalid
shared
invalid
shared
Notes:
— Don’t care or not applicable.
1. Asserted only for data cache hits to modified lines. Instruction cache lines can only be in the shared or invalid state.
2. HITM is never asserted while HIT is negated.
3. Transition occurs after any write to memory. Lines in “shared” MESI state are said to be in “writethrough” state. Those in “exclusive”
or “modified” MESI states are said to be in “writeback” state.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...